\doxysubsubsubsection{RCC PLL2 Clock Output }
\hypertarget{group___r_c_c___p_l_l2___clock___output}{}\label{group___r_c_c___p_l_l2___clock___output}\index{RCC PLL2 Clock Output@{RCC PLL2 Clock Output}}
\doxysubsubsubsubsubsection*{Macros}
\begin{DoxyCompactItemize}
\item 
\Hypertarget{group___r_c_c___p_l_l2___clock___output_gad1a8a81a015f275a253b4d399c0016b9}\label{group___r_c_c___p_l_l2___clock___output_gad1a8a81a015f275a253b4d399c0016b9} 
\#define {\bfseries RCC\+\_\+\+PLL2\+\_\+\+DIVP}~RCC\+\_\+\+PLLCFGR\+\_\+\+DIVP2\+EN
\item 
\Hypertarget{group___r_c_c___p_l_l2___clock___output_ga06627c6c5a9c03fafd82d1bbb8916dd8}\label{group___r_c_c___p_l_l2___clock___output_ga06627c6c5a9c03fafd82d1bbb8916dd8} 
\#define {\bfseries RCC\+\_\+\+PLL2\+\_\+\+DIVQ}~RCC\+\_\+\+PLLCFGR\+\_\+\+DIVQ2\+EN
\item 
\Hypertarget{group___r_c_c___p_l_l2___clock___output_ga23a9f811301522d6b81ad0b1cc249d1e}\label{group___r_c_c___p_l_l2___clock___output_ga23a9f811301522d6b81ad0b1cc249d1e} 
\#define {\bfseries RCC\+\_\+\+PLL2\+\_\+\+DIVR}~RCC\+\_\+\+PLLCFGR\+\_\+\+DIVR2\+EN
\end{DoxyCompactItemize}


\doxysubsubsubsubsection{Detailed Description}
